1. Field of the Invention
The invention relates to a debugging method, and particularly, to an accurate and efficient debugging method for a digital signal processor (DSP) development board.
2. Description of the Related Art
FIG. 1 shows the architecture of a conventional board platform 100. Embedded cores such as MPU or DSP cores are typically used in a conventional embedded system. A hardware emulator platform such as board platform 100 of FIG. 1 is typically utilized to trace bugs and estimate performance during core development. In the board platform 100, a processor 110 operates at frequency PCLK, and a debugging interface 130 operates at frequency TCK. Instructions executed by the processor 110 are selected from one of two sources via a prefetch 106. In normal mode, instructions sent from the instruction memory 122 are selected and passed to the processor 110. In debugging mode, the debugging interface 130 fetches a debugging program via a JTAG interface using a scan chain. The debugging program is first buffered in an instruction transfer register (ITR) 104, and then passed to the processor 110 by the prefetch 106. The debugging interface 130 is typically coupled to a debugger 140 or an external computer host. Thus, operations of the processor 110, including stop, step-by-step run, interruption point configuration, and memory accessibility can be fully controlled. Furthermore, a plurality of registers 112 implemented in the processor 110, are externally accessible via the debugging interface 130 as well as the main memory 120.
FIG. 2 is a flowchart of a conventional debugging method. The left side represents operations of the processor 110 at the frequency PCLK. In step 200, the board platform 100 is triggered by a trigger signal to enter a debugging mode. The processor 110 first stops the current normal operation, and waits until execution of all instructions queued in the pipelines 114 is complete. In step 202, the processor 110 enters a recursive waiting state, to wait for a debugging instruction to be passed from the ITR 104. On the other hand, when the board platform 100 enters the debugging mode in step 200, the debugging interface 130 processes step 212 to send externally input debugging instructions to the ITR 104. In step 214, when a debugging instruction is filled in the ITR 104, the debugging interface 130 delivers a ready signal to the processor 110, causing the processor 110 to exit the waiting state in step 202 and proceed to step 204. The debugging interface 130 subsequently processes step 216, an empty loop, to wait for an execution successful signal. In step 204, the processor 110 reads and executes the debugging instruction from the ITR 104. During the empty loop, any instruction associated data or parameters available in the data transfer register (DTR) 102, are read by the processor 110. In step 206, an execution successful signal is delivered when the processor 110 completes execution of the debugging instruction, and the debugging interface 130, in response, exits the waiting loop of step 216. Subsequently, in step 218, the debugging interface 130 issues a clear signal to indicate the current debugging instruction execution cycle has concluded. The debugging interface 130 then returns to step 212, to wait for the next debugging instruction to be sent from the debugging interface 130. The processor 110 simultaneously returns to step 202 to wait for another debugging instruction when conclusion of execution cycle is confirmed in step 208.
Because the frequencies PCLK and TCK are not identical, both parties rely on the waiting loops for handshake synchronization. Steps 202 to 218 are referred to as a round, during which only one debugging instruction can be input and executed to process only a predetermined amount of data. If the debugger 140 wants to write massive data to the data memory 124, a plurality of rounds are required to sequentially process the massive data, inefficiently consuming significant time and system resource. Thus, a debugging method for improving the efficiency is desirable.